The present invention generally pertains to emitter-coupled logic circuits and is particularly directed to an improvement in master-slave flip-flops.
Master-slave flip-flops are useful in various electronic circuits, such as a toggle flip-flop or a shift register, for example. A typical prior art master-slave flip-flop is shown in FIG. 1.
A master-slave flip-flop includes a master latch circuit 10 and a slave latch circuit 11. Complementary clock signals CLK and CLK are provided on lines 13 and 14 respectively from a clock buffer circuit 15 to control the operation of the master-slave flip-flop. During one clock signal interval the master latch circuit 10 is enabled to enter data provided by complementary data input signals D and D received at complementary data input terminals 17 and 18 respectively, while the data provided by complementary output signals Q and Q at complementary output terminals 20 and 21 of the slave latch circuit 11 remains unchanged. During the next complementary clock signal interval, the entered data is transferred from the latch circuit 10 to the data output terminals 20, 21 of the slave latch circuit 11.
The master latch circuit 10 includes a differential pair of first and second bipolar transistors Q1 and Q2 having their bases respectively coupled to lines 13 and 14 for receiving the complementary clock signals CLK and CLK. The collector of the transistor Q1 is coupled to the emitters of a differential pair of third and fourth bipolar transistors Q3 and Q4. The collector of the transistor Q2 is coupled to the emitters of a differential pair of fifth and sixth bipolar transistors Q5 and Q6. The basis of the transistors Q3 and Q4 are connected respectively to the complementary data input terminals 17 and 18.
The master latch circuit 10 further includes an emitter-follower pair of seventh and eighth bipolar transistors Q7 and Q8. The base of the transistor Q7 is coupled to the collectors of transistors Q3 and Q5. The base of transistor Q8 is coupled to the collectors of the transistors Q4 and Q6. The emitters of the transistors Q7 and Q8 are cross-coupled respectively to the bases of the transistors Q6 and Q5.
In the slave latch circuit 11 the transistors Q1', Q2', Q3', Q4', Q5', Q6', Q7', and Q8' are connected in the same manner as the corresponding numbered transistors Q1, Q2. . .Q8 in the master latch circuit 10, except that the bases of the transistors Q3' and Q4' are connected respectively to the emitters of the transistors Q7 and Q8 in the master latch circuit 10, the collector of the transistor Q2' is connected to the emitters of the transistors Q3' and Q4', the collector of the transistor Q1' is connected to the emitters of the transistors Q5' and Q6', and the emitters of the transistors Q7' and Q8' in the slave latch circuit 11 also are connected respectively to the complementary output terminals 20 and 21.
Referring to the master latch circuit 10, when the clock signal CLK is high and the clock signal CLK is low, transistor Q1 is rendered conductive so as to enable the transistors Q3 and Q4 to respond to the complementary input data signals D and D, by being driven to different logic conditions.
During the complementary clock interval, when the clock signal CLK is low and the clock signal CLK is high, the transistor Q2 is rendered conductive so as to enable the transistors Q5 and Q6 to latch the input data signals from the collectors of transistors Q3 and Q4 onto the emitters of transistors Q7 and Q8.
The slave latch circuit operates in the same manner to transfer the data signals from the emitters of the transistors Q7 and Q8 through to the complementary output terminals 20 and 21.
This typical master-slave flip-flop includes a total of sixteen transistors.
It is an object of the present invention to provide a master-slave flip-flop that is significantly less complex than typical prior art master-slave flip-flops.